(1) Field of the Invention
The invention relates to the general field of silicon integrated circuits, more particularly to Dynamic Random Access Memories and capacitors used therein.
(2) Description of the Prior Art
Dynamic Random Access Memories (DRAMs), as used in silicon integrated circuits, represent semiconductor devices that offer information storage at very high densities. These high densities are a consequence of the fact that the basic cell of a DRAM (wherein a single bit of information is stored) comprises a single Field Effect Transistor (FET) and a capacitor. The minimum capacitance required for the basic cell to operate efficiently is about femtofarads. This implies that the capacitor, rather than the FET, will be the limiting factor in determining how small the DRAM's basic cell can be made.
Capacitance value can be increased in any of three ways: the dielectric layer may be made thinner, the dielectric constant may be increased, and the area of the electrodes may be increased. The first two ways are limited by the availability of materials with suitable properties such as breakdown strength, high frequency characteristics, etc. so that most of the work to reduce the physical size of the capacitor in a DRAM cell has concentrated on increasing the effective area of the electrodes without increasing the amount of space within the integrated circuit that is taken up by the capacitor.
One of the geometries that has been successfully used to increase the effective area of the capacitor electrodes is to shape the capacitor in the form of a rectangular prism, at least one of whose surfaces is dimpled in some way such as rectangular or cylindrical depressions. The cradle-type capacitor is an example of this and is the geometry on which the present invention is based.
Dennison (U.S. Pat. No. 5,292,677 Mar. 8, 1994) describes processes that relate primarily to the DRAM cell as a whole, but also includes an example of a cradle-type capacitor. This is illustrated in FIG. 1. Shown in schematic cross-section is a single DRAM cell comprising an FET with source and drain electrodes, 5 and 4 respectively, a layer of gate oxide 3 and a gate electrode 6. Said gate electrode, when seen in plan view (not shown) has the shape of a hollow rectangle. One side of said hollow rectangle rests on gate oxide layer 6 while the opposite side rests on field oxide layer 2. The interior of the hollow rectangle is filled with layer 9 of polycrystalline silicon (poly) which is heavily doped (as symbolized by the small bubble-like dots) and serves as a bottom electrode for the DRAM capacitor while at the same time contacting source region 5.
Continuing reference to FIG. 1, said bottom electrode has been coated with dielectric layer 7 followed by a second layer of poly 8 which serves as the top electrode of the capacitor. The dip in the center of layers 7, 8, and 9 has a cradle-like appearance, hence the name cradle-like capacitor. In the Dennison process this dip is the result of layers 7, 8, and 9 following the natural contours of the structure, particularly the interior of the hollow rectangle. Thus it is relatively limited in extent and so increases the effective area of the capacitor electrodes by only a relatively small amount.